Commonly assigned U.S. Pat. No. 6,594,772, issued Jul. 15, 2003, of which I am a co-inventor, discloses a single integrated circuit chip having clock circuitry for supplying clock waves to many loads on the chip. The chip includes several clock node circuits at different locations on the chip and clock coupling circuitry connected between a clock wave output and input of adjacent clock nodes. Each clock node circuit and the clock coupling circuitry are arranged for maintaining a predetermined phase relation between the clock wave output and input of adjacent clock nodes.
In one embodiment, the clock node circuits and the clock coupling circuits include feedback arrangements for maintaining the predetermined phase relation. The clock wave inputs and outputs of the nodes are connected so there is no direct feedback from the clock wave outputs and inputs of any of the different clock nodes.
In another embodiment, circuitry connected to be responsive to the clock waves at spatially displaced first and second nodes on the chip (a) compares the relative phases of the clock waves at the spatially displaced nodes, and (b) derives a signal.
Clock waves derived at disparate locations on the single integrated circuit chip of the co-pending application have substantially the same phase, or have predictable, stable phase differences. One embodiment of the device of the co-pending application is particularly adapted for use on a single relatively large integrated circuit e.g., 2 centimeters on a side, operating at a high clock frequency e.g., more than 1.0 gigahertz (GHz), wherein effects of semiconductor processing, as well as temperature and voltage variations as a function of time and/or space are minimized. The circuitry of the co-pending application is particularly adapted for resolving problems associated with clock skew. Circuitry for deriving the signal indicative of clock skew quality of the chip clock circuitry includes: (a) an additional clock node, (b) an additional coupling circuit responsive to a clock wave at the first node, and (c) a phase detector arrangement. The additional clock node responds to a clock wave derived from the additional coupling circuit. The phase detector arrangement responds to a clock wave at the second node and the clock wave output of the additional node to derive the clock skew quality signal.
Another aspect of the previously mentioned patent relates to clock circuitry for supplying clock waves to many loads on a single integrated circuit chip, wherein the clock circuitry includes several clock nodes at different locations on the chip and clock coupling circuitry connected between adjacent clock nodes. Each clock node includes (a) a clock wave input, (b) a clock wave output and (c) feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave input and clock wave output of the particular node. The clock coupling circuitry maintains a predetermined phase relation between the output and input of the adjacent clock nodes on the single chip.
In the previously mentioned patent, clock circuitry for supplying clock waves to many loads on a single integrated circuit chip comprises several clock nodes at different locations on the chip and clock coupling circuitry connected between a clock wave output and input of adjacent clock nodes. Each clock node includes an arrangement for maintaining a predetermined phase relation between clock waves at the clock wave input and clock wave output of the particular node. Each clock coupling circuit includes a feedback loop for maintaining a predetermined phase relation between the clock wave output of a first of the adjacent nodes and the clock wave input of a second of the adjacent nodes.
I have now realized that many of the principles of the previously mentioned patent are applicable, with modification, to arrangements including plural integrated circuit chips having interconnected clock circuitry.